details of u-boot reading support for efusA9 emmc

      details of u-boot reading support for efusA9 emmc

      I'm trying to add reading support for emmc on efusA9 to u-boot from V3.0

      The diff below to fsimx6.c board file seems to work as it enables reading a file from an emmc partition,
      but I'm quite puzzled about the details.
      • The devicetree patch explicitly mentions vmmc-supply, allthough there doesn't seem to be an equivalent in the board file for adding this.
      • Is a bus width of 8 needed or desirable for just reading or is this only for additional stuff?
        (WLAN or other RF modems (like mentioned in the board file comments))
      • The pad configuration of the reset button in the device tree is 0x1B071, a value,
        that isn't completely explained by kosagi.com/w/index.php?title=D…ce_Tree_Naming_Convention
        What does this mean to achive and is it actually sufficient just to replace it with IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(NO_PAD_CTRL)) in u-boot?
      • Does the reset pin need additional initialization?

      Difference-File

      1. --- 0-fsimx6.c 2016-10-25 16:00:54.544988678 +0300
      2. +++ fsimx6.c 2016-10-26 12:56:25.999273652 +0300
      3. @@ -475,6 +475,24 @@
      4. IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
      5. };
      6. +/* configuration for efusa9 emmc */
      7. +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
      8. + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), /* used here as in usdhc3_pads, in linux devicetree it's 0x17071 */
      9. + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), /* used here as in usdhc3_pads; in linux devicetree it's 0x10071 */
      10. + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
      11. + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
      12. + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
      13. + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
      14. + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
      15. + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
      16. + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
      17. + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
      18. + /* Reset eMMC, active low */
      19. + IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(NO_PAD_CTRL)), /* ? in linux devicetree it's 0x1B071 */
      20. +};
      21. +
      22. +
      23. +
      24. struct fsl_esdhc_cfg esdhc_cfg[] = {
      25. {
      26. .esdhc_base = USDHC1_BASE_ADDR,
      27. @@ -629,6 +647,25 @@
      28. for on-board EMMC. This may also optionally be used for WLAN or
      29. other RF modems in the future. */
      30. + switch (fs_nboot_args.chBoardType) {
      31. + case BT_EFUSA9:
      32. + SETUP_IOMUX_PADS(usdhc3_emmc_pads);
      33. + ccgr6 |= (3 << 6);
      34. + index = 2;
      35. + break;
      36. + }
      37. +
      38. + // do something with reset pin?
      39. +
      40. + writel(ccgr6, &mxc_ccm->CCGR6);
      41. +
      42. + esdhc_cfg[index].sdhc_clk = mxc_get_clock(esdhc_cfg[index].sdhc_clk);
      43. + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
      44. +
      45. + if (ret)
      46. + return ret;
      47. +
      48. +
      49. return 0;
      50. }
      51. #endif

      domologic wrote:

      The devicetree patch explicitly mentions vmmc-supply, allthough there doesn't seem to be an equivalent in the board file for adding this.

      The VMMC supply is a non-switchable supply. So it is not necessary to switch it on, it is always on.

      Is a bus width of 8 needed or desirable for just reading or is this only for additional stuff?

      The higher buswidth can be used for higher access speed. However I would try with 4 bits first and only when this is fully working, switch to 8 bits.

      The pad configuration of the reset button in the device tree is 0x1B071, a value,
      that isn't completely explained by kosagi.com/w/index.php?title=D…ce_Tree_Naming_Convention

      Why is this not explained? All bits are fully described in the list there.

      What does this mean to achive and is it actually sufficient just to replace it with IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(NO_PAD_CTRL)) in u-boot?

      This value is the pin configuration, i.e. whether the pin uses a pull-up resistor, the speed requirements, the drive strength, and so on. If you just give NO_PAD_CTRL, then these settings are set to 0, which is usually not what you want. So no, using NO_PAD_CTRL is not sufficient. If you do not want to give the hex value, all necessary defines are available in arch/arm/inlcude/asm/imx-common/iomux-v3.h

      Does the reset pin need additional initialization?

      It should be configured as in Linux. The rest is done by the SDHC controller.

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