i2c on armStone A9r2

To have an I2C available instead of SPI on pins 16 and 17 was intended. But at the current state it is only possible through a SoftwareI2C with pins 16 and 17 configured as GPIOs.
If you don't have a touch controller you can use the hardware I2C bus on the Hirose 6 pin connector.

Best Regards
Your F&S Support Team

When will these pins 16/17 be available for I2C in device tree? Is this possible anytime or not (then we will have to change our hardware what is in beta state)?

Kind regards

The pins 16/17 are available on the connector. They can be used as GPIO etc. or as (bitbangig/SW)i2c too. This makes no difference as the i2c bitbangig driver uses these pins just as simple GPIOS.
So in both cases there are no changes on the hardware it's just a software feature. This will be set in the device tree.
For example on armstonea9 we are using a software i2c for the audio chip. The device tree nodes looks like this:

i2c node:

iomux controller:

Best Regards
Your F&S Support Team

Dear Support-Team,

is it possible to use the SX825x touch controller on the i2c5 instead of i2c2? If yes we can reduce a connector from our board to the 6 pin connector on armstoneA9r2 and use the pin 16/17 from the feature connector. Do we have to move the following code in armstonea9r2dlq.dtsi i2c2 section to a i2c5 section?

Thanks and kind regards.

Hmm, probably that was not completely clear before, but I2C5 is a bit-banging I2C on armStoneA9r2 that is located on the LVDS connector. It is *not* the one on pins 16/17 on the feature connector. If you want to have another bit-banging I2C on pins 16/17, you first have to define it in the device tree. We have no pre-defined node for this, yet. The example above from my colleague was taken from armStoneA9 (without r2), just to show how easy a bit-banging I2C can be set up. Please do not take these settings verbatim on armStoneA9r2, it will not work.

Please note that for this touch controller, you also need two additional GPIOs for Reset and IRQ. And you have to configure these GPIOs in the fragment you quoted above in entries interrupt-parent, interrupts and reset-gpio.

Please also note that touch traffic is rather high, so using a bit-banging I2C bus is not a very good solution and may cause very high CPU load. The dedicated 6-pin touch connector has a real hardware I2C bus on it. So this will not cause any significant CPU load.

Your F&S Support Team

I tried to define my own bit-banging I2C on the GPIO pins 16/17 on an armStoneA9r2, as supposed here. But had no luck yet. I see no appropriate i2c bus after booting the linux kernel.

Here is my modification of the shipped armstonea9r2qdl.dtsi.

I disabled SPI_A by commenting out
//#define CONFIG_ARMSTONEA9R2_SPI_A
in armstonea9r2dl.dts

Any hint what is wrong is welcome

Thanks and kind regards

Michael Frommberger

Dear Mr. Frommberger,

normally this configuration should work. I tried it and i see in the /dev directory i2c-6. This i2c-6 is the new Bitbanging I2C (i2c_gpio). Do you get any error messages?

Your F&S Support Team