Reset reason in U-Boot

    Hello,


    we are using the PicoCoreMX8MM and I would like know the reset reason of the system in U-Boot.
    Mainly I want to distinguish between Power-On-Reset and Software-Reset (reboot/reset).

    I would like to use this information for stability monitoring after an update. So SW-Reset would increment the bootcount, but POR won't.


    I get the reset-reason from U-Boot with get_reset_cause() or get_imx_reset_cause(), but they always indicate a POR, even after a reset from U-Boot or reboot from Linux.

    I have read that a lot of boards implement the SW-Reset by telling the PMIC to reset everything, so from the CPU point of view, this is the same as a "real" POR.


    How is the SW-Reset mechanism implemented on F&S boards?
    Also via PMIC?


    So I guess my main question is:

    Is it possible to distinguish between "real" Power-On-Resets and SW-Resets (reset/reboot from U-Boot/Kernel)?


    Thanks and best regards,
    Stefan

    Hello,


    a software reset will cause the CPU to pull the WDOG_B of the external PMIC. The PMIC will then pull the POR for the CPU, so the reset cause in perspective of the CPU will always be POR.

    A way to distinguish a "real" POR from a SW-Reset would be to access the RESETSRC (0x29) register of the PMIC. You can look up the register in the datasheet for the BD71847 under chapter "3.3.10 Reset Source Indicators". If you need that value in the RootFS, you could read that register in UBoot and set the reset_cause for bdinfo to that value under board/F+S/common/fs_fdt_common.c.


    After Power-On:

    Code
    1. PicoCoreMX8MM-LPDDR4 # i2c dev 3
    2. Setting bus to 3
    3. PicoCoreMX8MM-LPDDR4 # i2c md 0x4b 0x29 1
    4. 0029: 80

    After SW-Reset (UBoot or Linux):

    Code
    1. PicoCoreMX8MM-LPDDR4 # i2c dev 3
    2. Setting bus to 3
    3. PicoCoreMX8MM-LPDDR4 # i2c md 0x4b 0x29 1
    4. 0029: 40


    A HW-Reset can't be distinguished from a Power-On though. I hope the information helps.



    Your F&S Support Team