Using non-volatile memory on the M33 core without the A35 core

    Hello,


    Am I correct in understanding that the picocore8ulp does not provide any non-volatile memory accessible to the M33 core without involving the A35 core?


    Regarding the SD Card B interface: SD_B_DATA0 and SD_B_DATA1 are routed through GPIOF, which I believe makes them unusable during suspend-to-RAM mode of the A35 core. Is that correct?


    Is there any non-volatile memory available to the M33 core built into the i.MX8ULP? If not, what pins or interfaces could I use to connect an SD card directly to the M33 core?


    Thanks in advance for any insights.

    Hello Saturnion ,


    For the Cortex-M, I would primarily recommend using non-volatile memory via the SPI interface.

    At the moment, we are working on a new redesign of the PCore8ULP, which will indeed allow a PSRAM or NAND memory to be connected to the FLEXSPI interface.


    An implementation using an SD interface would certainly be possible, but it would come with some challenges.

    I assume you are using the PicoCoreMX8ULP rev1.10, correct?


    You would need to ensure that the APD domain remains active during suspend, so that the peripherals in PBRIDGE4 are still accessible.

    In addition, the ATF would have to configure the XRDC so the Cortex-M is allowed to access the SD interface.


    As far as I know, the AP domain should remain active in DSL mode (define IMX8ULP_DSL_SUPPORT in atf-bl31), so that access would still be possible. In DSL mode, essentially only the clock for the Cortex-A gets gated.


    If you really want to use an SD interface, you can use SD_A (but only if Wi-Fi is not equipped).

    Alternatively, you can route the SDHC2 signals to the B2B connector through PTF, provided that the module is configured for RGB instead of MIPI-DSI.

    Best regards


    F&S Elektronik Systeme GmbH
    As this is an international forum, please try to post in English.
    Da dies ein internationales Forum ist, bitten wir darum, Beiträge möglichst in Englisch zu verfassen.

    Thank you for the quick reply, fs-support_CS .


    As you mentioned, I am using PicoCoreMX8ULP rev1.10.

    Could you please explain in more detail about using SD_A? From what I understand, it uses the PTF and PTD pins. Is it possible to access them directly from the M33 core without using rpmsg or something similar, but instead natively, just like I interact with PTA?

    Yes, the Cortex-M can access the SDHC peripherals. However, there are

    several considerations:


    - XRDC must be configured in the ATF (BL31) to allow the Cortex-M to

    access the corresponding SDHC interface.


    - The Cortex-M must ensure that the required peripheral clocks remain

    enabled. XRDC access must be managed accordingly.


    - Linux should ensure that its drivers do not attempt to use the clock

    while it is controlled by the Cortex-M.


    - For power management, the Cortex-M must keep the SDHC APD domain

    active if necessary, for example during Linux suspend or power-off

    states.


    - Either the Cortex-M or Linux must configure the PINMUX in the

    IOMUXC1 for the SDHC interface.


    To proceed, I need to know your current Board ID. You can check this in

    U-Boot via the debug log or with the fsimage command. You should see a

    line like:


    BOARD-ID: PCoreMX8ULP-FERT1.110


    or:


    => fsimage board-id

    PCoreMX8ULP-FERT1.110


    With this information, I can verify whether you can use the SDHC

    interface from the PTF or PTD domain.


    Best regards

    F&S Elektronik Systeme GmbH
    As this is an international forum, please try to post in English.
    Da dies ein internationales Forum ist, bitten wir darum, Beiträge möglichst in Englisch zu verfassen.