Posts by Bharath

Thank you for the information provided.

Additionally, I would like to request clarification regarding our SDIO setup for the Ezurio Sona TI351 Evaluation Kit.

We connected the Sona TI351 microSDIO Daughter Board to the J6 SD card connector on the F&S i.MX8ULP Evaluation Board to establish SDIO communication between the Sona TI351 module and the F&S board.

1.We also observed that the SDIO interface was disabled in the device tree. We changed the status from "disabled" to "okay" and rebuilt the image; however, the SDIO device is still not detected. The following message is reported in the debug console:

root@fsimx8ulp:~# dmesg | grep -iE "mmc1|sdio"

mmc1: SDHCI controller on 298e0000.mmc [298e0000.mmc] using ADMA

mmc1: Failed to initialize a non-removable card

Current device tree configuration:

&osm_sdio_a {

pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";

pinctrl-0 = <&pinctrl_usdhc1>;

pinctrl-1 = <&pinctrl_usdhc1>;

pinctrl-2 = <&pinctrl_usdhc1>;

pinctrl-3 = <&pinctrl_usdhc1>;

bus-width = <4>;

vmmc-supply = <&WCF_AMPERSAND®_sdio_a_pwr>;

vqmmc-supply = <&WCF_AMPERSAND®_sdio_a_pwr>;

status = "disabled";

};

2.Could you also confirm which connector should be used for the SDIO interface:

• J6 (SD Card Connector), or
• J11 (SD_B signals available on the board)?
• Which USDHC controller (usdhc0/usdhc1/usdhc2) is connected to J6.

Any guidance on the correct hardware connection and required device tree configuration would be greatly appreciated.

Thank you for your support.

Best regards,

Bharath K R

HI F&S Team,

I inserted the SD card into the OSM board at connector J6, but it is not being detected. Is any jumper configuration required to enable SD card detection?

Thanks.

I would like to clarify the SPI configuration in OSM.

There are two SPI interfaces, SPI-A and SPI-B. Are both interfaces controlled by either the Cortex-M33 or Cortex-A35?

HI F&S Team,

Thank you for the clarification regarding LPSPI4 and the RGB pin usage.

From the schematic, I can see that both SPI_A and SPI_B signals appear to be available:

• SPI_A_CS0M
• SPI_A_SDI
• SPI_A_SDO
• SPI_A_SCK

and

• SPI_B_CS0#
• SPI_B_SDI
• SPI_B_SDO
• SPI_B_SCK

Since SPI_A signals are routed on the connector, I would like to understand whether these signals can be used from Linux.

My understanding is that SPI_A is connected to the FlexSPI controller in the RT domain and is typically intended for QSPI flash devices. However, because the SPI_A signals are available in the schematic, could you please clarify:

1. Is it possible to access SPI_A as a general-purpose SPI interface from Linux?
2. If yes, what device tree node and pinmux configuration should be used?
3. If SPI_A cannot be used from Linux, which routed SPI interface would you recommend for Linux userspace access?

I am asking because LPSPI4 pins PTF8-PTF11 are associated with the RGB interface and are not accessible on the PCoreBBDSI board.

Thanks

Hi F & S Team,

Could you please help clarify the following points regarding the Cortex-M33 firmware and RTOS integration?

1. Is FreeRTOS being used on the Cortex-M33 core? If so, which version of FreeRTOS is currently in use?

2. We were unable to locate the Cortex-M33 source files within the Yocto build environment. Could you please provide the location of these source files and share the steps required to build and compile the M33 firmware?

3. Is the M33 firmware provided as a precompiled binary that is packaged and flashed along with the Linux image, or is it generated as part of the Yocto build process?

4. Could you also clarify where the RTOS configuration is defined within the Yocto build and from which source or repository the RTOS is integrated?

Your guidance on the above points would be greatly appreciated.

Hi F&S Team,

We are using the FS 8ULP OSM-SF (HW Rev. 1.10) on the starter kit (ADP-OSM-BB + PicoCoreBBDSI).

In Linux, we currently see:

• /dev/ttyLP0 → OSM UART_CON (working on baseboard J8)
• /dev/ttyLP1 → OSM UART_A (DTS: lpuart6)

According to the OSM hardware documentation, UART_A is available on lands B13 (TX) and A14 (RX).

From the ADP-OSM-BB documentation, our understanding is:

• PicoCore UART_A (J8) is mapped from OSM UART_CON (D22/D23), not from OSM UART_A.
• OSM UART_A (B13/A14) does not appear to be routed to J8, J9, or J10 on the PicoCoreBBDSI.

Could you please clarify the following?

1. Is OSM UART_A (/dev/ttyLP1) routed to any connector on the starter kit?

2. Can you confirm whether J3B is only a schematic symbol representing the OSM land interface and not a physical connector on the board?

3. OSM UART_A (B13/A14) → Linux ttyLP1 Which connector/pins on the ADP and PicoCoreBBDSI is it routed to, if any? Or is it not routed at all?

   
   

We need clarification on how the OSM UART signals are routed through the adapter board to the PicoCoreBBDSI baseboard so that we can complete the device tree configuration correctly.

Attachments

• ADP schematic: J1 (for reference image osm-j1 connector) showing UART_A/B/C/D signal names.
• ADP schematic: SERIAL / level shifter showing OSM lands (e.g., D13, D22, B13, etc.).

Note: On the SERIAL schematic page, the J3B block appears to be a schematic symbol representing the OSM land interface only. We do not see a physical J3B connector on the board.

Thanks