From b1b4137477f40d192f814ca456f490cd1e0893f2 Mon Sep 17 00:00:00 2001 Message-Id: From: Hartmut Keller Date: Tue, 3 May 2016 15:21:26 +0200 Subject: [PATCH] Use F&S DDR3 settings arch/arm/mach-mx6/mx6_mmdc.c changes DRAM setings on the fly depending on the bus frequency. Unfortunately the initialization of the MMDC can only read the register values of the MMDC itself, but not the DDR3 settings that were sent (in the bootloader) as commands to the RAM chips. Therefore it needs to know some hard-coded values that must be the same as in the bootloader. Modify the settings to reflect the F&S RAM settings, do not use the fixed NXP settings anymore. This should make the whole RAM system more stable. FIXME: On F&S boards, these values should be passed via NBootArgs to the kernel. Using fix values bears the risk of inconsistent settings in bootloader and kernel and also can not represent all possible combinations as they depend on CPU type (D/Q or S/DL) and board (armStoneA9, QBlissA9, efusA9, PicoMODA9). For example we always activate On-Die-Termination (ODT), but it is only required on armStoneA9 and PicoMODA9. So the RAM energy consumption is unnecessary high on efusA9 and QBlissA9. --- arch/arm/mach-mx6/mx6_mmdc.c | 19 ++++++++++++++++++- 1 files changed, 18 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-mx6/mx6_mmdc.c b/arch/arm/mach-mx6/mx6_mmdc.c index 907e8aa..1ce1363 100644 --- a/arch/arm/mach-mx6/mx6_mmdc.c +++ b/arch/arm/mach-mx6/mx6_mmdc.c @@ -92,10 +92,18 @@ static unsigned int ddr_type; unsigned long ddr3_dll_mx6q[][2] = { {0x0c, 0x0}, {0x10, 0x0}, +#if 1 + /* F&S Settings from NBoot */ + {0x1C, 0x02088032}, + {0x1C, 0x00008033}, + {0x1C, 0x00408031}, + {0x1C, 0x09308030}, +#else {0x1C, 0x04088032}, {0x1C, 0x0408803a}, {0x1C, 0x08408030}, {0x1C, 0x08408038}, +#endif {0x818, 0x0}, }; @@ -113,10 +121,19 @@ unsigned long ddr3_calibration[][2] = { unsigned long ddr3_dll_mx6dl[][2] = { {0x0c, 0x0}, {0x10, 0x0}, + +#if 1 + /* F&S Settings from NBoot */ + {0x1C, 0x00008032}, + {0x1C, 0x00008033}, + {0x1C, 0x00008031}, + {0x1C, 0x05208030}, +#else {0x1C, 0x04008032}, {0x1C, 0x0400803a}, {0x1C, 0x07208030}, {0x1C, 0x07208038}, +#endif {0x818, 0x0}, }; @@ -220,7 +237,7 @@ unsigned long irqs_used_mx6dl[] = { MX6Q_INT_PERFMON1, }; -int can_change_ddr_freq(void) +static inline int can_change_ddr_freq(void) { return 1; } -- 1.7.4.4