Setup specific display with F&S Boards

How to setup a specific display on F&S boards?

The displays will be setup in the device tree. Our device trees are configured for our default displays:

• LVDS (old: CHI MEI G070Y2 / new: J070WVTC0211)
• LCD (ET070080DH6)

If you want to setup your specific display, it is mandatory to have the display datasheet. There are all necessary informations for setup. Below you can find a chart explaining timings of a display.

[IMG:http://processors.wiki.ti.com/images/e/e4/Lcd_datasheet_to_linux.jpg]

First of all I will explain how to setup a LVDS display.

LVDS Display:

First of all you have to open your device tree file (.dts) of your specific board, e.g. armstonea9dl.dts.

There you will find an entry which looks like below:

1. At the beginning you have to choose the mapping of the signals. You can choose between spwg and jeida, in the source code (above) you find the explanation what is the difference. You can get the mapping information from the display datasheet.
2. BPP is bits per pixel, you can take the default value 32.
3. PIX_FMT is the pixel format. RGB666 means 18 Bit data lines - 6 red, 6 green and 6 blue. E.g. if you have 24 bit data lines then it should be RGB24.
4. DATA_WIDTH correlate to PIX_FMT if you have 18 bit data lines then setup 18, if you have 24 bit data lines then 24.
5. The last part is the timing configuration.
   • clock-frequency is the pixel clock of the display in MHz, by default 33,5 MHz.
   • hactive is the horizontal active time (solution), by default 800, because display solution is 800x480.
   • vactive is the vertical active time (solution), by default 480, because display solution is 800x480.
   • hfront-porch is the time between the end of valid data and the beginning of the sync pulse in horizontal direction.
   • hback-porch historically refers to the period of time between the end of the sync pulse and the beginning of valid data in horizontal direction.
   • hsync-len indicating the start of the next line in horizontal direction.
   • vback-porch historically refers to the period of time between the end of the sync pulse and the beginning of valid data in vertical direction.
   • vfront-porch is the time between the end of valid data and the beginning of the sync pulse in vertical direction.
   • vsync-len indicating the start of the next line in vertical direction.
   • hsync-active means if 1 = hsync is active high, 0 means active low.
   • vsync-active means if 1 = hsync is active high, 0 means active low.
   • de-active means if 1 = de is active high, 0 means active low.
   • pixelclk-active means if 1 = pixelclk data on positiv edge, 0 means negative edge.

Normally in the display datasheet there is a parameter called H/V-SYNC-PERIOD. This parameter is the whole period of the display, you can calculate it.

HSYNC_PERIOD = hactive + hfront-porch + hback-porch + hsync-len

VSYNC_PERIOD = vactive + vfront-porch + vback-porch + vsync-len

If you can´t read out the front-porch, back-porch or syn-len then split it, so that the sum of the single parameters is equal to SYNC_PERIOD.

After everything is setup then go to the top of your dts file and change it to

#define CONFIG_ARMSTONEA9_MXCFB0 DISPLAY_LVDS0

After that you can recompile your device tree

make armstonea9dl.dtb

And install it on your board.

LCD Display:

For the LCD display there are two possibilities, for the i.MX 6 CPU, you have to open your device tree file (.dts) of your specific board, e.g. armstonea9dl.dts and the LCDIF driver mxc_lcdif.c in drivers/video/fbdev/mxc. If you have an i.MX6SX or i.MX6UL/ULL CPU e.g. efusA9X, you just have to open your device tree file (.dts).

In the device tree you will find the following entry:

If you have an i.MX 6 CPU (e.g. armstonea9dl), then you have setup the display timings via the MODE_STR, see below.

1. BPP is bits per pixel, you can take the default value 32.
2. PIX_FMT is the pixel format. RGB666 means 18 Bit data lines - 6 red, 6 green and 6 blue. E.g. if you have 24 bit data lines then it should be RGB24.
3. MODE_STR belongs to a string which you can find in the mxc_lcdif.c. Default string is LCD-ET070080. This string implies the display timings.

• You can have a look in mxc_lcdif.c, if you're lucky there is a string which has the correct timings for your display. If not, you have to add an entry with you specific display timings.
• If you have to create own display specific timings, then you have to add an entry. The struct fb_videomode has the following parameters:

1. name is a character pointer which is optional.
2. refresh is the refresh rate of the display and it is also optional.
3. xres = hactive is the horizontal active time (solution), by default 800, because display solution is 800x480.
4. yres = vactive is the vertical active time (solution), by default 480, because display solution is 800x480.
5. pixclock is the pixel clock of the display in pico seconds. s = 1 / f => = 10⁶ / MHz
6. left margin = hback-porch historically refers to the period of time between the end of the sync pulse and the beginning of valid data in horizontal direction.
7. right margin = hfront-porch is the time between the end of valid data and the beginning of the sync pulse in horizontal direction.
8. upper margin = vback-porch historically refers to the period of time between the end of the sync pulse and the beginning of valid data in vertical direction.
9. lower margin = vfront-porch is the time between the end of valid data and the beginning of the sync pulse in vertical direction.
10. hsync_len indicating the start of the next line in horizontal direction.
11. vsync-len indicating the start of the next line in vertical direction.
12. sync you can take a look to include/uapi/linux/mxcfb.h for possibilities.
13. vmode is normally FB_VMODE_NONINTERLACED. You can have a look to include/uapi/linux/fb.h for possibilities.
14. flag normally 0

Normally in the display datasheet there is a parameter called H/V-SYNC-PERIOD. This parameter is the whole period of the display, you can calculate it.

HSYNC_PERIOD = hactive + hfront-porch + hback-porch + hsync-len

VSYNC_PERIOD = vactive + vfront-porch + vback-porch + vsync-len

If you can´t read out the front-porch, back-porch or syn-len, then split it, so that the sum of the single parameters is equal to SYNC_PERIOD.

After everything is setup go to the top of your dts file and change it to

#define CONFIG_ARMSTONEA9_MXCFB0 DISPLAY_LCD

After that you can recompile your device tree and your kernel

make armstonea9dl.dtb

make uImage

And install kernel and device tree it on your board.

If you have an i.MX 6SX or an i.MX 6UL/ULL CPU (e.g. efusa9x) then you have to setup the display timings in device tree, see below.

The timings are the same like LVDS above.

1. BPP is bits per pixel, you can take the default value 32.
2. PIX_FMT is the pixel format. RGB666 means 18 Bit data lines - 6 red, 6 green and 6 blue. E.g. if you have 24 bit data lines then it should be RGB24.
3. DATA_WIDTH correlate to PIX_FMT if you have 18 bit data lines then setup 18, if you have 24 bit data lines then 24.
4. The last part is the timing configuration.

• clock-frequency is the pixel clock of the display in MHz, by default 33,5 MHz.
• hactive is the horizontal active time (solution), by default 800, because solution of display is 800x480.
• vactive is the vertical active time (solution), by default 480, because solution of display is 800x480.
• hfront-porch is the time between the end of valid data and the beginning of the sync pulse in horizontal direction.
• hback-porch historically refers to the period of time between the end of the sync pulse and the beginning of valid data in horizontal direction.
• hsync-len indicating the start of the next line in horizontal direction.
• vback-porch historically refers to the period of time between the end of the sync pulse and the beginning of valid data in vertical direction.
• vfront-porch is the time between the end of valid data and the beginning of the sync pulse in vertical direction.
• vsync-len indicating the start of the next line in vertical direction.
• hsync-active means if 1 = hsync is active high, 0 means active low.
• vsync-active means if 1 = hsync is active high, 0 means active low.
• de-active means if 1 = de is active high, 0 means active low.
• pixelclk-active means if 1 = pixelclk data on positiv edge, 0 means negative edge.

Normally in the display datasheet there is a parameter called H/V-SYNC-PERIOD. This parameter is the whole period of the display, you can calculate it.

HSYNC_PERIOD = hactive + hfront-porch + hback-porch + hsync-len

VSYNC_PERIOD = vactive + vfront-porch + vback-porch + vsync-len

If you can´t read out the front-porch, back-porch or syn-len then split it, so that the sum of the single parameters is equal to SYNC_PERIOD.

After everything is setup, then go to the top of your dts file and change it to

#define CONFIG_EFUSA9X_MXCFB0 DISPLAY_LCD

After that you can recompile your device tree

make efusa9x.dtb

And install it on your board.

HDMI Display:

First of all you have to open your device tree file (.dts) of your specific board, e.g. armstonea9dl.dts.

There you will find an entry which looks like below:

1. BPP is bits per pixel, you can take the default value 32.
2. PIX_FMT is the pixel format. RGB24 means 24 Bit data lines - 8 red, 8 green and 8 blue.
3. MODE_STR contains the solution and the refresh rate.

Normally these parameters are optional, because the HDMI gets the information via edid (Extended Display Identification Data).

After everything is setup then go to the top of your dts file and change it to

#define CONFIG_ARMSTONEA9_MXCFB0 DISPLAY_HDMI

After that you can recompile your device tree

make armstonea9dl.dtb

And install it on your board.

Your F&S Support Team