FS 8ULP OSM-SF - 1080p Display capability, 1080p60 Video Encode

    Hello,


    quick question about the graphics-capabilities of the i.MX8ULP.

    On the website it says that it is capable of 1080p60 video encoding.

    See: FS 8ULP OSM-SF » F&S Elektronik Systeme GmbH (fs-net.de)


    Is this true, if yes, how?


    There is nothing mentioned about video encoding in the datasheet.

    In chapter 66 "LCD Interface (LCDIF/DCNANO)" the supported display formats all stop at 1280x768 (WXGA).

    The i.MX8ULP has the DCNano graphics controller and the corresponding linux driver (dcnano-kms.c) limits the size to 1280x1280.


    Am I missing something?
    Is the i.MX8ULP capable of driving an 1920x1080 (1080p) panel?


    Thank you and best regards,
    Stefan

    Hello WaSt ,


    Unfortunately, the 8ULP does not contain a VPU and therefore no hardware-supported video decoding/encoding.


    Chapter 66.1 describes the dedicated interfaces DPI/DBI for LCDs.

    Please refer to chapter 61 MIPI-DSI Host Controller (MIPI-DSI) and chapter 66.2

    According to the reference manual DCNANO supports 1920x1080 @ 60fps via MIPI-DSI.

    So the i.MX8ULP is capable of driving an 1920x1080 Panel over MIPI-DSI.

    best regards,

    Claudio Senatore

    Hi Claudio,


    Thank you for your fast response.


    Where does it say that the DCNano is capable of 1920x1080 @ 60fps?



    Here is the display architecture of the i.MX8ULP.
    As I understand it, the display controller (DCNano) feeds the DSI Host Controller via DPI or DBI.

    So the DSI Host can only output what the display controller supplies.


    And according to the tables 574-576 in Chapter 66.1 the display controller can only output up to 1280x768.


    In 66.2 it says that the LCDIF is capable of 1920x1080 @ 60fps for linear formats, but as I understand it, the LCDIF is a different, more powerful display controller than the DCNano. And the i.MX8ULP has the DCNano display controller.


    The Linux kernel drm drivers also reflect that, as there are drivers for the dcnano (/drivers/gpu/drm/imx/dcnano) and for the lcdif (/drivers/gpu/drm/imx/lcdif(v3)).
    In these drivers the dcnano limits the size to 1280x1280 (see function dcnano_kms_prepare() in dcnano-kms.c) and the lcdif to 1920x1920 (see function lcdif_crtc_bind() in lcdif-crtc.c).


    So even if the DCNano would be capable of 1080p60, the corresponding linux driver limits the size to 1280x1280.


    So I think it is not possible to drive a 1920x1080 display or am I missing something?


    Best regards,
    Stefan

    Hello WaSt ,


    You are correct, although a maximum display size of 1080p is specified (see Table 578), it also refers to the chip-specific LCDIF information.

    Unfortunately, we are currently unable to test an FHD display to confirm this.


    If the advertised display formats match not only the dedicated DPI and DBI for IO, but also DPI/DBI for MIPI-DSI, then 1080p@60 will not work.

    Based on the Linux documentation, the values for height and widht are used for the framebuffer. It is possible to find out the system behavior by adjusting the values.


    I am trying to contact NXP to get a clear answer and will get back to you.

    Hello again,


    just as a followup to the linux driver topic.
    I changed the max. width and height in the dcnano driver to allow 1920x1080. The size checks are then successful, but the driver is unable to find a pll clock rate for the provided drm modes.

    The connected eDP-panel (connected via bridge) returns two modes:

    1. 1920x1080 @ 60Hz - 152570 kHz pixelclock

    2. 1920x1080 @ 40Hz - 101710 kHz pixelclock


    Here is the kernel output:



    This output is generated in the function dcnano_crtc_find_pll_clock_rate() in dcnano-crtc.c as it doesn't find a valid div value for the pll.


    Are there any restrictions on the possible pixelclocks of the dcnano display controller?


    Thank you and best regards,
    Stefan