I tried to access external hardware over the SPI bus.
Running a lightly modified spi_test.c let some strange timing diagram appear on the logic analizer.
8 bits/word sending 3 bytes give not 3*8*2 baud: I expected the clock would be:
The LA shows:
I use gpio 41 as CS0 which is assigned in the structure spi_ioc_transfer.pad
Trying to change clock phase or polarity cause an error message.
Change the bits/word works but it unusable, we need 8/word
The timing between lowering CS0 and rising clock is very small - few ns
The clock low phase between two bytes is very small - fw ns
The connected chip (CMX865A) is not responding.