Use SPI device pins as GPIO

dgrechi · Jan 10th 2017

Hi,

I'm trying to use pins 12, 14, 16, 17 (of the 66 pins connector) as GPIO output.
First I've used the /sys/class/gpio interface.
Then I've tested a C program that directly writes into the registers.
The result is the same.
I can only change the status of pin 14.
Pins 12, 16, 17 are always high.

Any suggestion?

This is my test C program:

C

#include <stdio.h>
#include <stdlib.h>
#include <errno.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <errno.h>
#include <string.h>
#include <stdint.h>
#include <unistd.h>
////////////////////////////////////////////////////////////////////////////
#define IOMUXC 0x020E0000
//////////////////////////////////////////////////////// GPIO2_IO26 (EIM_RW)
#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x0104
#define GPIO2_IO26_MUX IOMUXC_SW_MUX_CTL_PAD_EIM_RW
#define GPIO2_IO26_POS 26
/////////////////////////////////////////////////////// GPIO3_IO16 (EIM_D16)
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 0x0090
#define GPIO3_IO16_MUX IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16
#define GPIO3_IO16_POS 16
/////////////////////////////////////////////////////// GPIO3_IO17 (EIM_D17)
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 0x0094
#define GPIO3_IO17_MUX IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17
#define GPIO3_IO17_POS 17
/////////////////////////////////////////////////////// GPIO3_IO18 (EIM_D18)
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 0x0098
#define GPIO3_IO18_MUX IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18
#define GPIO3_IO18_POS 18
////////////////////////////////////////////////////////////////////////////
#define GPIO2_BASE 0x020A0000
#define GPIO3_BASE 0x020A4000
#define GPIOx_DR 0x0000
#define GPIOx_GDIR 0x0004
////////////////////////////////////////////////////////////////////////////
static volatile uint32_t *iomux;
static volatile uint32_t *gpio2;
static volatile uint32_t *gpio3;
////////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv)
{
int fd ;
printf("\n");
/////////////////////////////////////// obtain handle to physical memory
if ((fd = open ("/dev/mem", O_RDWR | O_SYNC) ) < 0)
{
printf("Unable to open /dev/mem: %s\n", strerror(errno));
return -1;
}
//////////////////////////////////////////////////// map IOMUX registers
iomux = (uint32_t *)mmap(0, 0x1000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, IOMUXC);
if ((int32_t)iomux < 0)
{
printf("IOMUX mmap failed: %s\n", strerror(errno));
exit(1);
}
///////////////////////////////////////////// select GPIO2_IO26 function
*(iomux + GPIO2_IO26_MUX/4) = 0x5;
///////////////////////////////////////////// select GPIO3_IO16 function
*(iomux + GPIO3_IO16_MUX/4) = 0x5;
///////////////////////////////////////////// select GPIO3_IO17 function
*(iomux + GPIO3_IO17_MUX/4) = 0x5;
///////////////////////////////////////////// select GPIO3_IO18 function
*(iomux + GPIO3_IO18_MUX/4) = 0x5;
////////////////////////////////////////////////// unmap IOMUX registers
if ((munmap((void *)iomux, 0x1000)) < 0)
{
printf("IOMUX munmap failed: %s\n", strerror(errno));
exit(1);
}
//////////////////////////////////////////// map GPIO2 control registers
gpio2 = (uint32_t *)mmap(0, 0x1000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, GPIO2_BASE);
if ((int32_t)gpio2 < 0)
{
printf("GPIO2 mmap failed: %s\n", strerror(errno));
exit(1);
}
//////////////////////////////////////////// map GPIO3 control registers
gpio3 = (uint32_t *)mmap(0, 0x1000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, GPIO3_BASE);
if ((int32_t)gpio3 < 0)
{
printf("GPIO3 mmap failed: %s\n", strerror(errno));
exit(1);
}
///////////////////////////////////////////// setup GPIO2_IO26 as output
*(gpio2 + GPIOx_GDIR/4) = *(gpio2 + GPIOx_GDIR/4) | 1<<GPIO2_IO26_POS;
///////////////////////////////////////////// setup GPIO3_IO16 as output
*(gpio3 + GPIOx_GDIR/4) = *(gpio3 + GPIOx_GDIR/4) | 1<<GPIO3_IO16_POS;
///////////////////////////////////////////// setup GPIO3_IO17 as output
*(gpio3 + GPIOx_GDIR/4) = *(gpio3 + GPIOx_GDIR/4) | 1<<GPIO3_IO17_POS;
///////////////////////////////////////////// setup GPIO3_IO18 as output
*(gpio3 + GPIOx_GDIR/4) = *(gpio3 + GPIOx_GDIR/4) | 1<<GPIO3_IO18_POS;
////////////////////////////////////////////////////// toggle GPIOx_IOxx
while (1)
{
*(gpio2 + GPIOx_DR/4) = *(gpio2 + GPIOx_DR/4) ^ 1<<GPIO2_IO26_POS;
*(gpio3 + GPIOx_DR/4) = *(gpio3 + GPIOx_DR/4) ^ 1<<GPIO3_IO16_POS;
*(gpio3 + GPIOx_DR/4) = *(gpio3 + GPIOx_DR/4) ^ 1<<GPIO3_IO17_POS;
*(gpio3 + GPIOx_DR/4) = *(gpio3 + GPIOx_DR/4) ^ 1<<GPIO3_IO18_POS;
usleep(250000);
}
}

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fs-support_PH · Jan 11th 2017

Hi,

The pins are used for SPI by default. So the internal iomux-controller of the SOC is configured to bring the SPI signals to the pads. Pin 14 works because it is used as chip select which is in fact a GPIO.
The other pins can't work, especially when testing with /sys/class...

The common way to configure the iomux controller is by editing the device tree.
You have to deactivate SPI_A and configure every of the four pins as GPIO. (Also No. 14 must be configured because it will also be disabled when deactivating SPI_A.)

This is how the configuration is done in the device tree:

- Deactivate SPI_A: remove/comment CONFIG_ARMSTONEA9_SPI_A in arch/arm/boot/dts/armstonea9dl.dts
(Solo/DualLite) or arch/arm/boot/dts/armstonea9q.dts (Dual/Quad) depending on the processor you have.

- Open the file arch/arm/boot/dts/armstonea9qdl.dtsi and go to the ' pinctrl_hog_1' node. Here you can see
some pads that are configured as GPIO. Here you have to set every pin.
E.G. for pin 14 it looks like this:

MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x80000000

- Recompile the devicetree and install it on the board.

Best Regards
Your F&S Support Team

fs-support_PJ · Jan 11th 2017

Dear Mr. Dgrechi,

thanks for this hint. I checked the pins and found out that we have something wrong in our document "armStoneA9-GPIO-ReferenceCard_eng.pdf". The GPIO3IO16, GPIO3IO17, GPIO3IO18 were wrong documented. I fixed this document and uploaded it to our server. Now you can download the newest version from our homepage. Download link below:
https://www.fs-net.de/assets/d…PIO-ReferenceCard_eng.pdf

Best Regards
Your F&S Support Team

dgrechi · Jan 11th 2017

Thank you for the reply.

I'm using fsimx6-V2.1 without Device Tree.
So I'm trying to directly program the i.mx6 resgisters.

I've configured the "ALT5" (0x5) function in the iomux registers related to 12, 14, 16, 17 pins (EIM_D16, EIM_RW, EIM_D17, EIM_D18 respectively): this should configure pins as GPIO.

Then I've set the output direction through the GPIOx_GDIR registers.

But, as I mentioned, I can't change the EIM16, EIM_D17, EIM_D18 status.

What is missing?

dgrechi · Jan 11th 2017

Ok, thank you!

I've read now the fixed documentation.

I'll try with the new pin numbers.

dgrechi · Jan 12th 2017

Now everything works!

Best Regards

Use SPI device pins as GPIO

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