GPIO on armstonea9r2dl

Dear Mr. Schubert,

i think there is a small bug with this gpio. Did you compiled the DeviceTree by yourself or did you use the precompiled armstonea9r2dl.dtb?

Your F&S Support Team

Dear Mr Schubert,

you have to insert one line in the DeviceTree that the GPIO 64 work.

1.) Go to the armstonea9r2qdl.dtsi file
2.) Search after the node iomuxc
3.) Then search within that node after the comment /* RTC_IRQ */ or MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28
4.) Then add a new line with the following String "MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x80000000"
It should be look like this.

/* RTC_IRQ */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0xb0b0

MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x80000000
>;

5.) Recompile it and download it to board. Now it should work.

Your F&S Support Team

Thanks, you too.

Your F&S Support Team

Hello,

I have the same issue with GPIO in armStoneA9r2 with V3.0, and V3.1 too.

I have modified armstonea9r2qdl.dtsi as said in #post13713, but I am still not able to toggle the value of any GPIO, pins are always high (I measure the voltage with a voltmeter).

Is this a known issue? There is a workaround for this?

Thanks in advance!

Please note that the settings above are only for GPIO 64. Other GPIOs may need other settings. Our device tree is configured for our default functions. So if you want to use a pin for GPIO, you have to make sure that this pin is not used for a dedicated function. Some functions can be activated and de-activated by setting a CONFIG macro. For example if you want to use the pins 4/6/8/10 of SPI_B as GPIO, then you can undefine CONFIG_ARMSTONEA9R2_SPI_B. Then these pins are not configured for SPI anymore.

Unfortunately not all pins can be freed by setting CONFIG macros. For example the pin VLCD_ON on the LVDS connector and the backlight connector is a single pad setting that has to be removed manually. We enhance the device tree from time to time to make as many configurations available as easy as possible.

If a pin is not configured for its dedicated function, then the pin is in most cases automatically configured as GPIO. However there are a few exceptions, where either the Reset setting is not the GPIO function or where the ROM loader of the CPU, NBoot or U-Boot have reconfigured the pin already to a different function. So to be sure, you should add a pad setting in the iomuxc part of the device tree that actually does configure the pin as GPIO. The node named "hoggrp-1" is suited for this. Here all pad settings are collected that do not belong to a more specific group of pins.

If you still have problems, then please give us an example of a pin that does not work. Include the pad settings in iomuxc and also show us the commands that you use to toggle the pin. Then we can check this here.

Your F&S Support Team

Hi,

I finally solved this issue.

Thank you!