I2C / TWI support in u-boot to read EEPROM on efusA9X

BrenkeM · Jul 31st 2017

Hello,

I need to read out a EEPROM-IC via I2C in u-boot. I noticed that there is no I2C support for the efusA9X module, see "No I2C used in U-Boot on F&S i.MX6 SoloX boards" (UBOOT/include/configs/fsimx6sx.h).

Is there a other board with the imx6sx processor or a source that provided support for the I2C bus, or what else can I do to communicate in u-boot with the EEPROM?

Thanks.

fs-support_HK · Jul 31st 2017

Yes, we currently do not need I2C in U-Boot and therefore we haven't activated it, yet. But there are quite a few drivers available, so you do not write the driver from scratch.

When you are on a dedicated I2C bus, then you can use drivers/i2c/mxc_i2c.c. This is the driver for all i.MX6 CPU variants. If you only can use regular GPIOs and need a bitbanging I2C, then drivers/i2c/soft_i2c.c may help. These drivers register with the generic i2C framework in drivers/i2c/i2c_core.c. This is the file that also provides the functions to be used from outside to access I2C.

Unfortunately I'm not exactly sure how I2C works in U-Boot. If there is some board-specific initialization required, you can add this function to board/F+S/fsimx6sx/fsimx6sx.c, where all our i.MX6-SoloX specific stuff is located. There you have to configure the pads used for I2C. I think the best way to learn how this works on i.MX6 is by looking at the NXP code itself, which is for example in board/freescale/mx6sabresd/mx6sabresd.c. Here they seem to initialize the I2C pads and then they call a function setup_i2c() which is defined in arch/arm/imx-common/i2c-mxv7.c.

Your own code that actually reads from I2C EEPROM can also be added to fsimx6sx.c, maybe in board_init() or board_late_init().

Your F&S Support Team

BrenkeM · Aug 1st 2017

Hello,

I edited board/F+S/fsimx6sx/fsimx6sx.c according board/freescale/mx6sabresd/mx6sabresd.c and arch/arm/include/asm/arch/mx6sx_pins.h (for the PADs).

I also enabled the i2c and the eeprom command in uboot for debugging.

I am able to compile UBOOT. But there is no way to access the I2C bus. Please give me a hint what is wrong or how I can check/debug my errors.

The hardware is fine. In LINUX the EEPROM can be read and write out of the box.

COMMANDS:

Code

setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x53, &i2c_pad_info0); (in board/F+S/fsimx6sx/fsimx6sx.c)
force_idle_bus: sda=1 scl=0 sda.gp=0x3 scl.gp=0x2
force_idle_bus: failed to clear bus, sda=1 scl=0

Code

efusA9X # i2c probe 0x53 ( in UBOOT)
Valid chip addresses:wait_for_sr_state: failed sr=81 cr=0 state=2020
i2c_init_transfer: failed for chip 0x53 retry=0
wait_for_sr_state: failed sr=81 cr=0 state=2020
i2c_init_transfer: failed for chip 0x53 retry=1
…
i2c_init_transfer: give up i2c_regs=021a0000

FILES:

Diff

--- /home/brenkem/svn/efusA9X/UBOOT/trunk/board/F+S/fsimx6sx/fsimx6sx.c 2017-07-11 16:15:31.801530806 +0200
+++ board/F+S/fsimx6sx/fsimx6sx.c 2017-08-01 15:19:48.381134339 +0200
@@ -44,6 +44,12 @@
#include <usb.h> /* USB_INIT_HOST, USB_INIT_DEVICE */
#include <malloc.h> /* free() */
+
+//////////////////////
+#include <i2c.h>
+#include <asm/imx-common/mxc_i2c.h>
+
+
/* ------------------------------------------------------------------------- */
#define NBOOT_ARGS_BASE (PHYS_SDRAM + 0x00001000) /* Arguments from NBoot */
@@ -95,6 +101,16 @@
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+/////////////////////////////////
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
struct board_info {
char *name; /* Device name */
unsigned int mach_type; /* Device machine ID */
@@ -317,6 +333,55 @@
/* Now RAM is valid, U-Boot is relocated. From now on we can use variables */
+/////////////////
+static struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ // I2C_C
+ .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 2)
+ },
+ .sda = {
+ // I2C_C
+ .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 3)
+ }
+};
+
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ // I2C_A
+ .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 0)
+ },
+ .sda = {
+ // I2C_A
+ .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 1)
+ }
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ // I2C_B
+ .i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | I2C_PAD,
+ .gp = IMX_GPIO_NR(2, 14)
+ },
+ .sda = {
+ // I2C_B
+ .i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | I2C_PAD,
+ .gp = IMX_GPIO_NR(2, 19)
+ }
+};
+
+
+
static iomux_v3_cfg_t const reset_pads[] = {
IOMUX_PADS(PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
@@ -775,6 +840,15 @@
setup_var("fdt", bi->fdt, 1);
setup_var("bootargs", "set_bootargs", 1);
+
+
+///////////////////////////
+//setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x53, &i2c_pad_info0);
+setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x53, &i2c_pad_info1);
+setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x53, &i2c_pad_info2);
+
+
+
return 0;
}
#endif

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---------------------------------------------

Diff

--- /home/brenkem/svn/efusA9X/UBOOT/STACCserver/trunk/include/configs/fsimx6sx.h 2017-07-20 13:24:09.185495621 +0200
+++ include/configs/fsimx6sx.h 2017-08-01 15:01:13.692821671 +0200
@@ -207,6 +207,11 @@
* I2C
************************************************************************/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define I2C_DELAY udelay(5)
+#define CONFIG_SYS_I2C_SPEED 100000
/************************************************************************
@@ -222,6 +227,14 @@
/************************************************************************
+ * EEPROM
+ ************************************************************************/
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 // 8-bit EEPROM page address
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
/************************************************************************
* Real Time Clock (RTC)
************************************************************************/
/* ###TODO### */
@@ -396,7 +409,10 @@
#undef CONFIG_CMD_DTT /* No digital thermometer and thermostat */
#define CONFIG_CMD_ECHO /* Have echo command */
#define CONFIG_CMD_EDITENV /* Allow editing of environment variables */
-#undef CONFIG_CMD_EEPROM /* No EEPROM support */
+
+//#undef CONFIG_CMD_EEPROM /* No EEPROM support */
+#define CONFIG_CMD_EEPROM /* EEPROM support */
+
#undef CONFIG_CMD_ELF /* No support to boot ELF images */
#define CONFIG_CMD_EXT2 /* Support for EXT2 commands */
#define CONFIG_CMD_EXT4 /* Support for EXT4 commands */
@@ -413,7 +429,10 @@
#undef CONFIG_CMD_GREPENV /* No support to search in environment */
#undef CONFIG_CMD_HASH /* No hash command */
#undef CONFIG_CMD_HWFLOW /* No switching of serial flow control */
-#undef CONFIG_CMD_I2C /* No I2C support */
+
+//#undef CONFIG_CMD_I2C /* No I2C support */
+#define CONFIG_CMD_I2C /* I2C support */
+
#undef CONFIG_CMD_IDE /* No IDE disk support */
#define CONFIG_CMD_IMI /* Image information (iminfo) */
#undef CONFIG_CMD_IMLS /* No support to list all found images */

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BrenkeM · Aug 1st 2017

UPDATE:

After changing the addr to 0x7F (see https://github.com/boundarydev…rogen6x/nitrogen6x.c#L915) I was able to access the i2c bus 0 and 2:
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);

The error from bus 0 (I2C_C) is still present. But the bus works:

Code

force_idle_bus: sda=1 scl=0 sda.gp=0x3 scl.gp=0x2
force_idle_bus: failed to clear bus, sda=1 scl=0

The bus number 1 is still not working, but the error message has changed to:

Code

efusA9X # i2c dev 1
efusA9X # i2c probe 0x53
Valid chip addresses:wait_for_sr_state: Arbitration lost sr=93 cr=80 state=2020
i2c_init_transfer: failed for chip 0x53 retry=0
wait_for_sr_state: Arbitration lost sr=93 cr=80 state=2020
i2c_init_transfer: failed for chip 0x53 retry=1
…
i2c_init_transfer: give up i2c_regs=021a4000

fs-support_HK · Aug 2nd 2017

I2C_B alias I2C3 is correct, this is on pads KEY_ROW4 and KEY_COL4. This is why this port works.
I2C_C alias I2C1 is correct, this is on pads GPIO1_IO00 and GPIO1_IO01. This is why this port works. Only your comment is wrong where you name this as I2C_A.
But I2C_A alias I2C2 is wrong. On our board this is on pads QSPI1B_DATA2 and QSPI1B_DATA3. This is why this port does not work. The pins that you defined are actually used for other signals on our board.

Your F&S Support Team

BrenkeM · Aug 3rd 2017

Thanks for your help. Now every thing is working great.

I configured all PADs as recommended. The error "force_idle_bus: sda=1 scl=0 sda.gp=0x3 scl.gp=0x2" and "force_idle_bus: failed to clear bus, sda=1 scl=0" are gone.
All i2c buses works in UBOOT.

Below the needed changed to enable I2C in UBOOT for the efusA9X / fsimx6sx: (NOTE that the 5µs delay is specific for my EEPROM)

Diff

--- ../u-boot-2014.07-fsimx6sx-V2.0/include/configs/fsimx6sx.h 2016-08-20 00:57:44.000000000 +0200
+++ include/configs/fsimx6sx.h 2017-08-02 12:56:35.869322396 +0200
@@ -198,7 +206,10 @@
/************************************************************************
* I2C
************************************************************************/
-/* No I2C used in U-Boot on F&S i.MX6 SoloX boards */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define I2C_DELAY udelay(5)
+#define CONFIG_SYS_I2C_SPEED 100000

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Diff

--- ../u-boot-2014.07-fsimx6sx-V2.0/board/F+S/fsimx6sx/fsimx6sx.c 2016-08-20 00:57:44.000000000 +0200
+++ board/F+S/fsimx6sx/fsimx6sx.c 2017-08-03 10:47:46.303261540 +0200
@@ -44,6 +44,10 @@
#include <usb.h> /* USB_INIT_HOST, USB_INIT_DEVICE */
#include <malloc.h> /* free() */
+#include <i2c.h>
+#include <asm/imx-common/mxc_i2c.h>
+
+
/* ------------------------------------------------------------------------- */
#define NBOOT_ARGS_BASE (PHYS_SDRAM + 0x00001000) /* Arguments from NBoot */
@@ -94,6 +99,11 @@
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
struct board_info {
char *name; /* Device name */
@@ -310,9 +324,48 @@
return 0;
}
/* Now RAM is valid, U-Boot is relocated. From now on we can use variables */
+// define I2C PADs for bus #0, #1, #2
+static struct i2c_pads_info i2c_pad_info0 = { // I2C_C; I2C1; Bus #0
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 0)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 1)
+ }
+};
+
+static struct i2c_pads_info i2c_pad_info1 = { // I2C_A; I2C2; Bus #1
+ .scl = {
+ .i2c_mode = MX6_PAD_QSPI1B_DATA3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_QSPI1B_DATA3__GPIO4_IO_27 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_QSPI1B_DATA2__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_QSPI1B_DATA2__GPIO4_IO_26 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 26)
+ }
+};
+
+static struct i2c_pads_info i2c_pad_info2 = { // I2C_B; I2C3; Bus #2
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | I2C_PAD,
+ .gp = IMX_GPIO_NR(2, 14)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | I2C_PAD,
+ .gp = IMX_GPIO_NR(2, 19)
+ }
+};
+
static iomux_v3_cfg_t const reset_pads[] = {
IOMUX_PADS(PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
@@ -771,6 +824,31 @@
setup_var("fdt", bi->fdt, 1);
setup_var("bootargs", "set_bootargs", 1);
+ // init i2c bus for uboot
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
return 0;
}
#endif

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BrenkeM · Aug 3rd 2017

Case closed. See above.

fs-support_HK · Aug 3rd 2017

Thanks for sharing your code with us.

Your F&S Support Team

I2C / TWI support in u-boot to read EEPROM on efusA9X

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