3.5 Inch display integration with efusA9

  • Hi everyone,


    I am trying to integrate this 3.5 display with efusA9 quad core platform. That display has exactly the same AC timing characteristics as your 3.5 inch display. I want to know please what are the correct kernel configuration for this 3.5 display?


    I know I have to change the following:


    1- I modified only these lines in this file --> linux-4.1.15-fus-Y1.0/arch/arm/boot/dts/efusa9q.dts (I used LCD-ET035080 instead of the 7 inch display)

    Code
    1. /*
    2. * Configure LCD settings here (ignored if LCD is not used);
    3. * see drivers/video/fbdev/mxc/mxc_lcdif.c for possible LCD mode strings
    4. */
    5. #define CONFIG_EFUSA9_LCD_BPP 32
    6. #define CONFIG_EFUSA9_LCD_PIX_FMT "BGR666"
    7. #define CONFIG_EFUSA9_LCD_MODE_STR "LCD-ET035080"


    2- I looked as well into linux-4.1.15-fus-Y1.0/drivers/video/fbdev/mxc/mxc_lcdif.c file where the LCD-ET035080 defined


    Code
    1. {
    2. /* 320x240 @ 60 Hz , pixel clk @ 6.5MHz */
    3. "LCD-ET035080", 60, 320, 240, 153846, 68, 20, 18, 4, 20, 10,
    4. 0,
    5. FB_VMODE_NONINTERLACED,
    6. 0,
    7. },


    If you please have a look at the data sheet page 10 of my display, you will find it is exactly the same as your display at page 5. This means there is no difference between your display and my display and your configuration shall work.


    please what shall I change in order to get this 3.5 display to work?


    Thanks in advance

    Ahmed

  • If it has the same timings, then you have to do nothing. Just connect your display.


    Your F&S Support Team

    F&S Elektronik Systeme GmbH
    As this is an international forum, please try to post in English.
    Da dies ein internationales Forum ist, bitten wir darum, Beiträge möglichst in Englisch zu verfassen.

  • Hi,


    please I want to mention that, I did not change the LCD configurations in file "linux-4.1.15-fus-Y1.0/drivers/video/fbdev/mxc/mxc_lcdif.c" for your 3.5 LCD and here is actually the configuration I used:


    Code
    1. {
    2. /* 320x240 @ 60 Hz , pixel clk @ 6.5MHz */
    3. "LCD-ET035080", 60, 320, 240, 153846, 48, 20, 8, 4, 20, 10,
    4. 0,
    5. FB_VMODE_NONINTERLACED,
    6. 0,
    7. },

    Then I had no chance to get it to work.


    Please I want to mention also that my 3.5 LCD worked very well on the 7Ull efus module (single core), because the configurations were looking a little bit different than in efus Quad core module.


    So I actually changed the LCD settings in the dts file of efus7ull module "linux-4.1.15-fus-Y1.0/arch/arm/boot/dts/efusa7ul.dts" to -->


    (It was previously configured to your standard 7 inch display and I used this configuration for my 3.5 LCD)



    Then with that configuration above, everything worked on the 7ull module but I tried to use it as well for the quad core but no gain.


    There are 4 parameters "hsync-active" , "vsync-active" , "de-active" and "pixelclk-active" which I could not set them in the "mxc_lcdif.c" for the 3.5 inch display in the "LCD-ET035080" part which I posted up there.


    Thanks in advance,

    kind regards

  • Ah OK, now I understand.


    Yes, the LCD controllers are different on efusA9 (i.MX6DL/Q) and efusA7UL (i.MX6UL/ULL). So unfortunately the settings must also be done differently. The efusA7UL can have all parameters in the device tree. The efusA9 needs a setting in mxc_lcdif.c and just references it with the modestr entry, which is given with the CONFIG_EFUSA9_LCD_MODE_STR macro. So from a first view everything seems correct.


    But I'm not fully sure if the timings are really identical. Because in your data sheet, the back porch part always includes the sync time itself. But in our timings thy sync times are additional values. (The 20 and 10 at the end of the first parameter line in the array entry). In your case, the sync times actually do not matter, so using the default 20 for HSYNC and 10 for VSYNC should be OK. But then I think you need to subtract them from the back porch values, so you only have to set 68 - 20 = 48 for the Horizontal Back Porch and 18 - 10 = 8 as Vertical Back Porch.


    The SYNC polarities should be OK. If nothing is given in the value after the timings (line 4 above), then HSYNC and VSYNC are active low. Also the data is latched on the rising edge of the pixel clock, which is also the default case. So this matches your data sheet. DE is not used at all, so its polarity does not matter.


    Your F&S Support Team


    PS: Sorry for the late answer, but we were all on Embedded World 2019 in Nürnberg last week.

    F&S Elektronik Systeme GmbH
    As this is an international forum, please try to post in English.
    Da dies ein internationales Forum ist, bitten wir darum, Beiträge möglichst in Englisch zu verfassen.

  • Thanks for your reply.


    I have tried your suggestion as follows:


    * I modified the LCD string "LCD-ET035080" in this file linux-4.1.15-fus-Y1.0/drivers/video/fbdev/mxc/mxc_lcdif.c according to your values that you suggested -->

    Code
    1. {
    2. /* 320x240 @ 60 Hz , pixel clk @ 6.5MHz */
    3. "LCD-ET035080", 60, 320, 240, 153846, 48, 20, 8, 4, 20, 10,
    4. 0,
    5. FB_VMODE_NONINTERLACED,
    6. 0,
    7. },

    Please is it possible to provide the values to be written in mxc_lcdif.c file as I tried many times but no gain to get our LCD working?


    another question please, is your 3.5 LCD working with efusA9 Quad core module ?


    Thanks,

    Kind regards